1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof, and in particular to a chip size semiconductor package (CSP) and a fabrication method thereof.
2. Background of the Related Art
FIG. 1 illustrates a conventional thin small on-line package (TSOP). The problems encountered in the conventional thin small on-line package are described in the U.S. Pat. No. 5,363,279 ('279). FIG. 2 illustrates a bottom lead package (BLP) of the '279 patent, which is assigned to the same assignee as the present invention. The BLP has a disadvantage in that the reliability of the solder joint is decreased compared to the TSOP. In the conventional BLP, if there is not a solder joint between a lead and a printed circuit board (PCB), a delamination and a cracking problem occur in the solder joint. In addition, since the conventional TSOP and BLP shown in FIGS. 1 and 2 are fully sealed by a molding compound, it is difficult to effectively radiate the heat generated in the semiconductor chip.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.